1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and, more particularly, to a semiconductor system configured to perform a write leveling operation and an operating method thereof.
2. Description of the Related Art
Generally, input of signals to a dynamic random access memory (DRAM) or a semiconductor circuit is performed using a clock signal of a semiconductor system. If the clock signal is changed by external and/or internal noise components, a signal input may become abnormal. Furthermore, if a clock signal margin is not secured due to incompleteness of a configuration circuit, the signal input may be recognized as an abnormal input signal, which may affect an output signal. In an existing system configuration, an abnormal output signal from a logic circuit cannot be determined, which may become the cause of a malfunction of another logic circuit using the abnormal output signal as an input signal. A case where whether the state of an abnormal output signal has a “high” level or “low” level cannot be determined is called a meta-stable state.
Continuous increases in the operating speed of semiconductor systems require higher speed, data transmission rate and lower power operation between semiconductor devices in the semiconductor systems. A common method for increasing the operating speed and reducing the power consumption of semiconductor devices has been to increase a frequency of a clock.
If the frequency of the clock is increased, a data strobe signal DQS is also increased with the same frequency. If the data strobe signal DQS with a high frequency cannot be used in a semiconductor device, the data strobe signal DQS is divided by a DQS frequency divider and used in the semiconductor device. The DQS frequency divider may use a division control signal generated based on a clock signal. The division control signal is sensitive to a change in the process, voltage, and temperature (PVT), and may be controlled so that it is enabled prior to a write preamble section. During the write preamble section the data strobe signal DQS maintains a low level for 1 clock before data is output. In this case, a problem may occur. This is described in detail with reference to FIG. 1.
FIGS. 1A to 1C are diagrams illustrating a meta-stable state.
FIG. 1A shows a DQS buffer circuit for buffering external data strobe signals DQS_t/DQS_c that are differentially inputted from an external device.
In FIG. 1A, the DQS buffer circuit may buffer the external data strobe signals DQS_t and DQS_c in response to a buffer enable signal BUFF_EN and output internal data strobe signals DS and DSB.
FIG. 1B shows a DQS frequency divider circuit for generating first to fourth data strobe signals IDQS, QDQS, IDQSB, and QDQSB having different phases by dividing the internal data strobe signals DS and DSB. FIG. 1B may include first and second flip-flops FF1 and FF2.
FIG. 1C is a timing diagram showing the operations of the DQS buffer circuit and the DQS frequency divider circuit shown in FIGS. 1A and 1B.
From FIG. 1C, it may be seen that the DQS buffer circuit and the DQS frequency divider circuit are enabled before the external data strobe signals DQS_t and DQS_c are inputted. In this case, if a noise is generated in a DQS channel (e.g., the Internal node DQS DVD_INT NODE of a DQS divider), the DQS buffer circuit amplifies the noise, and thus the DQS frequency divider circuit may malfunction due to the noise. In other words, when the noise is generated in the internal node DQS DVD_INT NODE of the DQS divider, the DQS frequency divider circuit enters into a meta-stable state. Accordingly, the DQS frequency divider circuit outputs a signal divided at an abnormal timing. As a result, there may be a problem in that a circuit using the divided data strobe signal malfunctions.
In order to solve such a problem, a division control signal may be controlled so that it is enabled in a write preamble section. However, in this case, there is a possibility that the DQS frequency divider circuit may enter the meta-stable state.
A training operation, such as write leveling, is required to control the division control signal so that it is enabled at a specific timing within a write preamble section. In general, in the performance specification of a semiconductor memory device, a domain crossing margin tDQSS between the data strobe signal and the clock signal is provided. Accordingly, the semiconductor memory device adopts a write leveling technology in which a skew between the data strobe signal and the clock signal is calibrated when performing a write operation. In such a write leveling operation, a phase between a clock signal and at least one of the strobe division signals based on a data strobe signal is detected, and the phase of the clock signal and the phase of an external data strobe signal are matched by controlling timing when the external data strobe signal is generated.